Entries tagged - "RPU"

• Designing a RISC-V CPU in VHDL, Part 22: Doom as a benchmark and adding Cache to RPU Jan 9, 2022
• Designing a RISC-V CPU in VHDL, Part 21: Multi-cycle execute for multiply and divide May 29, 2021
• Designing a RISC-V CPU in VHDL, Part 20: Interrupts and Exceptions Oct 3, 2020
• Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality Feb 13, 2020
• Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit Jul 16, 2019
• Designing a RISC-V CPU in VHDL, Part 17: DDR3 Memory Controller, Clock domain crossing Oct 21, 2018
• Designing a RISC-V CPU in VHDL, Part 16: Arty S7 RPU SoC, Block Rams, 720p HDMI Sep 26, 2018